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CY2DP1504
1:4 LVPECL Fanout Buffer with Selectable Clock Input
Features

Functional Description
The CY2DP1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1504 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.
Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to four LVPECL output pairs 30 ps maximum output-to-output skew 480-ps maximum propagation delay 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) Up to 1.5-GHz operation Synchronous clock enable function 20-pin thin shrunk small outline package (TSSOP) 2.5-V or 3.3-V operating voltage[1] Commercial and industrial operating temperature range
Logic Block Diagram
VDD VSS IN0 IN0# IN1 IN1# IN_SEL
100k
Q0 Q0# Q1 Q1# Q2 Q2# Q3 Q3#
VDD
100k
Q D
CLK_EN
Note 1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation Document Number: 001-56215 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 10, 2011
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Contents
Pinouts .............................................................................. 3 Absolute Maximum Ratings ............................................ 4 Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information...................................................... 10 Ordering Code Definition ........................................... 10 Package Dimension........................................................ 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14
Document Number: 001-56215 Rev. *F
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Pinouts
Figure 1. Pin Diagram - 20-Pin TSSOP Package
V SS CLK_EN IN_SEL IN0 IN0# IN1 IN1# NC NC V DD
1 2 3 4 5 6 7 8 9 10 CY2DP1504
20 19 18 17 16 15 14 13 12 11
Q0 Q0# V DD Q1 Q1# Q2 Q2# V DD Q3 Q3#
Table 1. Pin Definitions Pin No. 1 2 Pin Name VSS CLK_EN Input Pin Type Power Ground Synchronous clock enable. Low-voltage complementary metal oxide semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL). When CLK_EN = Low, Q(0:3) outputs are held Low and Q(0:3)# outputs are held High Input clock select pin. LVCMOS/LVTTL; When IN_SEL = Low, the IN0/IN0# differential input pair is active When IN_SEL = High, the IN1/IN1# differential input pair is active LVPECL input clock. Active when IN_SEL = Low LVPECL complementary input clock. Active when IN_SEL = Low LVPECL input clock. Active when IN_SEL = High LVPECL complementary input clock. Active when IN_SEL = High No connection Power Output Output Power supply LVPECL complementary output clocks LVPECL output clocks Description
3
IN_SEL
Input
4 5 6 7 8,9 10,13,18 11,14,16,19 12,15,17,20
IN0 IN0# IN1 IN1# NC VDD Q(0:3)# Q(0:3)
Input Input Input Input
Document Number: 001-56215 Rev. *F
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CY2DP1504
Absolute Maximum Ratings
Parameter VDD VIN[2] VOUT[2] TS ESDHBM LU UL-94 MSL Supply voltage Input voltage, relative to VSS DC output or I/O voltage, relative to VSS Storage temperature Electrostatic discharge (ESD) protection (Human body model) Latch up Flammability rating Moisture sensitivity level At 1/8 in Description Condition Nonfunctional Nonfunctional Nonfunctional Non functional JEDEC STD 22-A114-B Min -0.5 -0.5 -0.5 -55 2000 Max 4.6
lesser of 4.0 or VDD + 0.4 lesser of 4.0 or VDD + 0.4
Unit V V V C V
150 -
Meets or exceeds JEDEC Spec JESD78B IC Latchup Test V-0 3
Operating Conditions
Parameter VDD TA tPU Supply voltage Ambient operating temperature Power ramp time Description Condition 2.5-V supply 3.3-V supply Commercial Industrial Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic). Min 2.375 3.135 0 -40 0.05 Max 2.625 3.465 70 85 500 Unit V V C C ms
Note 2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required.
Document Number: 001-56215 Rev. *F
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DC Electrical Specifications
(VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter IDD VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VID[3] VICM IIH IIL VOH VOL RP CIN Description Operating supply current Input high voltage, LVPECL input clocks IN0 and IN0#, IN1 and IN1# Input low voltage, LVPECL input clocks IN0 and IN0#, IN1 and IN1# Input high voltage, CLK_EN, IN_SEL Input low voltage, CLK_EN, IN_SEL Input high voltage, CLK_EN, IN_SEL Input low voltage, CLK_EN, IN_SEL Input differential amplitude Input common mode voltage Input high current, all inputs Input low current, all inputs LVPECL output high voltage LVPECL output low voltage Internal pull-up/pull-down resistance, LVCMOS logic inputs Input capacitance VDD = 3.3 V VDD = 3.3 V VDD = 2.5 V VDD = 2.5 V See Figure 2 on page 7 See Figure 2 on page 7 Input = VDD[4] Input = VSS[4] Terminated with 50 to VDD - CLK_EN has pull-up only IN_SEL has pull-down only Measured at 10 MHz; per pin 2.0[5] Terminated with 50 to VDD - 2.0[5] Condition All LVPECL outputs floating (internal IDD) Min - - -0.3 2.0 -0.3 1.7 -0.3 0.4 0.5 - -150 Max 61 VDD + 0.3 - VDD + 0.3 0.8 VDD + 0.3 0.7 1.0 VDD - 0.2 150 - Unit mA V V V V V V V V A A V V k pF
VDD - 1.20 VDD - 0.70 VDD - 2.0 VDD - 1.63 60 - 140 3
Notes 3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV. 4. Positive current flows into the input pin, negative current flows out of the input pin. 5. Refer to Figure 3 on page 7.
Document Number: 001-56215 Rev. *F
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AC Electrical Specifications
(VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter FIN FOUT VPP Description Input frequency Output frequency FOUT = FIN LVPECL differential output voltage peak Fout = DC to 150 MHz to peak, single-ended. Terminated with 50 to VDD - 2.0[6] Fout = >150 MHz to 1.5 GHz Propagation delay input pair to output pair Output duty cycle Output-to-output skew Device-to-device output skew Input rise/fall time < 1.5 ns (20% to 80%) 50% duty cycle at input Frequency range up to 1 GHz Any output to any output, with same load conditions at DUT Any output to any output between two or more devices. Devices must have the same input and have the same output load. Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz tJIT[10] Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), VID > 400 mV 50% duty cycle at input, 20% to 80% of full swing (VOL to VOH) Input rise/fall time < 1.5 ns (20% to 80%) Synchronous clock enable (CLK_EN) switched Low Synchronous clock enable (CLK_EN) switched High Condition Min DC DC 600 400 - 48 - - Typ - - - - - - - - Max 1.5 1.5 - - 480 52 30 150 Unit GHz GHz mV mV ps % ps ps
tPD
[7]
tODC[8] tSK1[9] tSK1 D[9]
PNADD
Additive RMS phase noise 156.25 MHz Input Rise/fall time < 150 ps (20% to 80%) VID > 400 mV
- - - - - - -
- - - - - - -
-120 -130 -135 -145 -153 -155 0.15
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps
tR, tF[11]
Output rise/fall time
-
-
300
ps
tSOD tSOE
Time from clock edge to outputs disabled Time from clock edge to outputs enabled
- -
- -
700 700
ps ps
Notes 6. Refer to Figure 3 on page 7. 7. Refer to Figure 4 on page 7. 8. Refer to Figure 5 on page 7. 9. Refer to Figure 6 on page 8. 10. Refer to Figure 7 on page 8. 11. Refer to Figure 8 on page 8.
Document Number: 001-56215 Rev. *F
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Figure 2. Input Differential and Common Mode Voltages
IN VID IN#
VA VICM = (VA + VB)/2 VB
Figure 3. Output Differential Voltage
Q VPP Q#
VOH
VOL
Figure 4. Input to Any Output Pair Propagation Delay
IN IN # QX Q X#
t PD
Figure 5. Output Duty Cycle
QX Q X#
tPW tPERIOD
tODC = tPW tPERIOD
Document Number: 001-56215 Rev. *F
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Figure 6. Output-to-Output and Device-to-Device Skew
QX Q X# Device 1 QY Q Y# tSK1 QZ Device 2 Q Z# tSK1 D
Figure 7. RMS Phase Jitter
Phase noise
Noise Power Phase noise mark
Offset Frequency f1 f2 Area Under the Masked Phase Noise Plot
RMS Jitter
Figure 8. Output Rise/Fall Time
QX 20% QX# tR
80% 80% VPP 20% tF
Document Number: 001-56215 Rev. *F
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CY2DP1504
Figure 9. Synchronous Clock Enable Timing
CLK_EN IN IN#
tSOD tPD tSOE
QX QX#
Document Number: 001-56215 Rev. *F
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Ordering Information
Part Number Pb-free CY2DP1504ZXC CY2DP1504ZXCT CY2DP1504ZXI CY2DP1504ZXIT 20-Pin TSSOP 20-Pin TSSOP tape and reel 20-Pin TSSOP 20-Pin TSSOP tape and reel Commercial, 0 C to 70 C Commercial, 0 C to 70 C Industrial, -40 C to 85 C Industrial, -40 C to 85 C Type Production Flow
Ordering Code Definition
CY 2DP15 04 ZX C/I T
Tape and reel Temperature range C = Commercial I = Industrial Pb-free TSSOP package Number of differential output pairs Base part number Company ID: CY = Cypress
Document Number: 001-56215 Rev. *F
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Package Dimension
Figure 10. 20-Pin Thin Shrunk Small Outline Package (4.40 mm Body) ZZ20
51-85118 *C
Document Number: 001-56215 Rev. *F
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Acronyms
Table 2. Acronyms Used in this Document Acronym ESD HBM JEDEC LVCMOS LVPECL LVTTL OE RMS TSSOP Description electrostatic discharge human body model Joint electron devices engineering council low-voltage complementary metal oxide semiconductor low-voltage positive emitter-coupled logic low-voltage transistor-transistor logic Output enable root mean square thin shrunk small outline package
Document Conventions
Table 3. Units of Measure Symbol C dBc GHz Hz k A F s mA ms mV MHz ns pF ps V W degree Celsius decibels relative to the carrier giga hertz hertz kilo ohm microamperes micro Farad microsecond milliamperes millisecond millivolt megahertz nanosecond ohm pico Farad pico second volts watts Unit of Measure
Document Number: 001-56215 Rev. *F
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Document History Page
Document Title: CY2DP1504 1:4 LVPECL Fanout Buffer with Selectable Clock Input Document Number: 001-56215 Revision ** *A ECN 2782891 2838916 Orig. of Change CXQ CXQ Submission Date 10/09/09 01/05/2010 New Datasheet. Changed status from "ADVANCE" to "PRELIMINARY". Changed from 0.34 ps to 0.25 ps maximum additive jitter in "Features" on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added tPU spec to the Operating Conditions table on page 3. Changed max IDD spec in the DC Electrical Specs table on page 4 from 60 mA to 61 mA. Change VOH in the DC Electrical Specs table on page 4: minimum from VDD - 1.15V to VDD - 1.20V; maximum from VDD - 0.75V to VDD - 0.70V. Removed VOD spec from the DC Electrical Specs table on page 4. Added RP spec in the DC Electrical Specs table on page 4. Min = 60 k, Max = 140 k. Added a measurement definition for CIN in the DC Electrical Specs table on page 4. Added VPP spec to the AC Electrical Specs table on page 5. VPP min = 600 mV for DC - 150 MHz and min = 400 mV for 150 MHz to 1.5 GHz. Changed letter case and some names of all the timing parameters in the AC Electrical Specs table on page 5 to be consistent with EROS. Lowered all additive phase noise mask specs by 3 dB in the AC Electrical Specs table on page 5. Added condition to tR and tF specs in the AC Electrical specs table on page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%). Changed letter case and some names of all the timing parameters in Figures 3, 4, 5, 6 and 8, to be consistent with EROS. Changed maximum additive jitter from 0.25 ps to 0.11 ps in "Features" on page 1 and in tJIT in the AC Electrical Specs table. Added note 3 to describe IIH and IIL specs. Removed reference to data distribution from "Functional Description". Changed RP for differential inputs from 100 k to 150 k in the Logic Block Diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the DC Electrical Specs table. Added max VID of 1.0V in DC Electrical Specs table. Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs table. Added "Frequency range up to 1 GHz" condition to tODC spec. Updated package diagram. Added Acronyms and Ordering Code Definition. Corrected Output Rise/Fall time diagram. Updated Phase jitter to 0.15ps max from 0.11ps max. Changed VIN and VOUT specs from 4.0V to "lesser of 4.0 or VDD + 0.4" Removed 200mA min LU spec, replaced with "Meets or exceeds JEDEC Spec JESD78B IC Latchup Test" Removed RP spec for differential input clock pins INX and INX#. Changed CIN condition to "Measured at 10 MHz". Changed PNADD specs for 1MHz, 10MHz, and 20MHz offsets. Removed tS and tH specs from AC specs table. Removed "Preliminary" status heading. Removed resistors from INx/INx# in Logic Block Diagram. Added Figure 9 to describe TSOE and TSOD. Post to external web. Description of Change
*B
3011766
CXQ
08/20/2010
*C *D
3017258 3100234
CXQ CXQ
08/27/2010 11/18/2010
*E
3135201
CXQ
01/12/2011
*F
3090938
CXQ
02/25/2011
Document Number: 001-56215 Rev. *F
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(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-56215 Rev. *F
Revised January 10, 2011
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